IBM POWER8 processor core microarchitecture

core microarchitecture B. Sinharoy J. A. Van Norstrand R. J. Eickemeyer H. Q. Le J. Leenstra D. Q. Nguyen B. Konigsburg K. Ward M. D. Brown J. E. Moreira D. Levitan S. Tung D. Hrusecky J. W. Bishop M. Gschwind M. Boersma M. Kroener M. Kaltenbach T. Karkhanis K. M. Fernsler The POWER8i processor is the latest RISC (Reduced Instruction Set Computer) microprocessor from IBM. It is fabricated using the company’s 22-nm Silicon on Insulator (SOI) technology with 15 layers of metal, and it has been designed to significantly improve both single-thread performance and single-core throughput over its predecessor, the POWER7A processor. The rate of increase in processor frequency enabled by new silicon technology advancements has decreased dramatically in recent generations, as compared to the historic trend. This has caused many processor designs in the industry to show very little improvement in either single-thread or single-core performance, and, instead, larger numbers of cores are primarily pursued in each generation. Going against this industry trend, the POWER8 processor relies on a much improved core and nest microarchitecture to achieve approximately one-and-a-half times the single-thread performance and twice the single-core throughput of the POWER7 processor in several commercial applications. Combined with a 50% increase in the number of cores (from 8 in the POWER7 processor to 12 in the POWER8 processor), the result is a processor that leads the industry in performance for enterprise workloads. This paper describes the core microarchitecture innovations made in the POWER8 processor that resulted in these significant performance benefits.